EMICRO 2018

20ª Escola Sul de Microeletrônica


SIM 2018

33º Simpósio Sul de Microeletrônica
2 a 5 de maio de 2018 - Curitiba/PR



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Dia 02 de maio - a partir das 19h00.

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Obs.: Membros do IEEE-CASS terão o jantar financiado pelo Capitulo IEEE CASS Rio Grande do Sul.

Programação

2 DE MAIO, QUARTA-FEIRA

  • Ministrante: Paulo Butzen

  • Instituição do Ministrante: FURG
  • Ministrante: Gabriel Rincón-Mora

  • Instituição do Ministrante: Georgia Institute of Technology

  • Biography: Prof. Gabriel A. Rincón-Mora is Fellow of the American National Academy of Inventors (NAI), Institute of Electrical and Electronics Engineers (IEEE), and Institution of Engineering and Technology (IET). He worked for Texas Instruments in 1994-2003, was an Adjunct Professor at the Georgia Institute of Technology (Georgia Tech) in 1999-2001, has been professor at the Georgia Institute of Technology since 2001, and has been visiting professor at National Cheng Kung University in Taiwan since 2011. His scholarly products in-clude 9 books, 4 book chapters, 42 patents, over 170 articles, over 26 commercial power-chip designs, and over 130 international speaking engagements. He was inducted into Georgia Tech's Council of Outstanding Young Engineering Alumni and named one of "The 100 Most Influential Hispanics" by Hispanic Business magazine. He received the National Hispanic in Technology Award from the Society of Hispanic Professional Engineers, Charles E. Perry Visionary Award from Florida International University, Commendation Certificate from the Lieutenant Governor of California, Orgullo Hispano and Hispanic Heritage awards from Robins Air Force Base, IEEE Service Award from the IEEE Circuits and Systems Society (CASS), IEEE Certificate of Appreciation from IEEE CASS, and two Thank a Teacher Certificates from Georgia Tech. He has served as Distinguished Lecturer, General Chair and Co-Chair, Technical Program Chair and Co-Chair, Associate Editor, Guest Editor and Co-Editor, Chapter Chair and Vice-Chair, International Liaison, Steering Committee Member, and Advisory Panel Member on multiple occasions for many IEEE and other international conferences and workshops.

    Lecture: Networked wireless microsensors can not only monitor and manage power consumption in small - and large - scale applications for space, military, medical, agricultural, and consumer markets but also add cost-, energy-, and life-saving intelligence to large infrastructures and tiny devices in remote and difficult-to-reach places. Ultra-small systems, however, cannot store sufficient energy to sustain monitoring, interface, processing, and telemetry functions for long. And replacing or recharging the batteries of hundreds of networked nodes can be labor intensive, expensive, and oftentimes impossible. This is why alternate sources are the subject of ardent research today. Except power densities are low, and in many cases, intermittent, so supplying functional blocks is challenging. Plus, tiny lithium-ion batteries and super capacitors, while power dense, cannot sustain life for extended periods. This talk illustrates how emerging microelectronic systems can draw energy from elusive ambient sources to power tiny wireless sensors.

  • Ministrante: Alyssa Apsel

  • Instituição do Ministrante: Cornell University

  • Biography: Alyssa Apsel is currently a Professor of Electrical and Computer Engineering and a Visiting Professor at Imperial College in London working on RF interfaces for implantable electronics. She received the B.S. from Swarthmore College in 1995 and the Ph.D. from Johns Hopkins University, Baltimore, MD, in 2002. She joined Cornell University in 2002, where the focus of her research is on power-aware mixed signal circuits and design for highly scaled CMOS and modern electronic systems. Her current focus is on low power radio for IoT and reconfigurable multi-standard radio to extend the reach of wireless communications. She has authored or coauthored over 100 refereed publications in related fields of RF mixed signal circuit design, ultra-low power radio, interconnect design and planning, photonic integration, and process invariant circuit design techniques resulting in eight patents and several pending patent applications. She received best paper awards at ASYNC 2006 and IEEE SiRF 2012, had a MICRO “Top Picks” paper in 2006, received a college teaching award in 2007, received the National Science Foundation CAREER Award in 2004, and was selected by Technology Review Magazine as one of the Top Young Innovators in 2004. She has also served as an Associate Editor of various journals including IEEE Transactions on Circuits and Systems I and II, as the chair of the Analog and Signal Processing Technical committee of ISCAS 2011, as Deputy Editor in Chief of Circuits and Systems Magazine, and on the Board of Governors of IEEE CAS.

    Tutorial: Although not everyone is a wireless designer, everyone seems to want to include a wireless interface on their chip or system. With the advent and exploding interest in IoT, the emphasis on making all data communication wireless has only increased. Some of these communication interfaces are interesting from a research point of view, and some are not. When overall power consumption and efficiency are of paramount interest, however, simply adding a wireless interface onto an otherwise low power sensing or computing chip may not be straightforward. In fact, the wireless interface is likely to consume the bulk of the power of these systems and overwhelm the power budget. With the range of technologies calling themselves low power wireless interfaces, it is no surprise that uninitiated system designers often choose the wrong one. The purpose of this tutorial is to demystify some of these choices and make it easier for designers whose focus is not on the RF interface to pick the correct technology for their applications and get started with simple designs. I will introduce the basic transceiver architectures for popular wireless candidates including: wake-up radios, low power UWB radios, NFC, backscatter radios, Bluetooth, and Zigbee. I will also discuss the advantages and disadvantages as well as potential applications for each. I will compare and contrast these radios with the end goal of enabling designers to make educated and intelligent decisions about which RF transceivers make sense for their applications in sensors, body area networks, IoT, implantables, or whatever they may be. Finally, attendees will walk through case studies and simple design problems and select suitable wireless interfaces for different applications.

  • Ministrante: Alyssa Apsel

  • Instituição do Ministrante: Cornell University

  • Biography: Alyssa Apsel is currently a Professor of Electrical and Computer Engineering and a Visiting Professor at Imperial College in London working on RF interfaces for implantable electronics. She received the B.S. from Swarthmore College in 1995 and the Ph.D. from Johns Hopkins University, Baltimore, MD, in 2002. She joined Cornell University in 2002, where the focus of her research is on power-aware mixed signal circuits and design for highly scaled CMOS and modern electronic systems. Her current focus is on low power radio for IoT and reconfigurable multi-standard radio to extend the reach of wireless communications. She has authored or coauthored over 100 refereed publications in related fields of RF mixed signal circuit design, ultra-low power radio, interconnect design and planning, photonic integration, and process invariant circuit design techniques resulting in eight patents and several pending patent applications. She received best paper awards at ASYNC 2006 and IEEE SiRF 2012, had a MICRO “Top Picks” paper in 2006, received a college teaching award in 2007, received the National Science Foundation CAREER Award in 2004, and was selected by Technology Review Magazine as one of the Top Young Innovators in 2004. She has also served as an Associate Editor of various journals including IEEE Transactions on Circuits and Systems I and II, as the chair of the Analog and Signal Processing Technical committee of ISCAS 2011, as Deputy Editor in Chief of Circuits and Systems Magazine, and on the Board of Governors of IEEE CAS.

    Tutorial: Although not everyone is a wireless designer, everyone seems to want to include a wireless interface on their chip or system. With the advent and exploding interest in IoT, the emphasis on making all data communication wireless has only increased. Some of these communication interfaces are interesting from a research point of view, and some are not. When overall power consumption and efficiency are of paramount interest, however, simply adding a wireless interface onto an otherwise low power sensing or computing chip may not be straightforward. In fact, the wireless interface is likely to consume the bulk of the power of these systems and overwhelm the power budget. With the range of technologies calling themselves low power wireless interfaces, it is no surprise that uninitiated system designers often choose the wrong one. The purpose of this tutorial is to demystify some of these choices and make it easier for designers whose focus is not on the RF interface to pick the correct technology for their applications and get started with simple designs. I will introduce the basic transceiver architectures for popular wireless candidates including: wake-up radios, low power UWB radios, NFC, backscatter radios, Bluetooth, and Zigbee. I will also discuss the advantages and disadvantages as well as potential applications for each. I will compare and contrast these radios with the end goal of enabling designers to make educated and intelligent decisions about which RF transceivers make sense for their applications in sensors, body area networks, IoT, implantables, or whatever they may be. Finally, attendees will walk through case studies and simple design problems and select suitable wireless interfaces for different applications.

3 DE MAIO, QUINTA-FEIRA

  • Ministrante: Raphael Brum

  • Instituição do Ministrante: UFRGS
  • Ministrante: Ricardo Reis

  • Instituição do Ministrante: UFRGS

  • Biography: Full Professor at Instituto de Informática of the UFRGS (professor since 1979). Electrical Engineering from the UFRGS, Porto Alegre, Brazil, in 1978. Ph.D. degree from the Polytechnic Institute of Grenoble (INPG), France, January 1983. Member of IEEE CASS Distinguished Lecturer Program 2014/2015. Former member of the Microelectronics Committee and Computer Science Committee (two terms) of the National Council for Scientific and Technological Development (CNPq). His primary research interests include Physical Design Automation and Methodologies, CAD tools, Circuits Tolerant to Radiation, VLSI Design Methodologies and Microelectronics Education. More than 500 hundred papers in journals and conferences proceedings. He is also author or co-author of several books. Award as research of the year by the Science Foundation of Rio Grande do Sul, 2002. Silver Core award from IFIP. Meritorious Service Award 2015 by IEEE Circuits and Systems Society. Research level 1A of the CNPq (Brazilian National Science Foundation). Head of several research projects. Past head of the Graduate Program on Microelectronics Graduate Program (two terms) and Computer Science (two terms) at UFRGS. Professor and Advisor at the Microelectronics and Computer Science Graduate Programs at UFRGS. General Chair or Program Chair of several conferences like the IFIP/IEEE VLSI-SoC, IEEE ISVLSI, IEEE LASCAS, Symposium on Integrated Circuits and Systems Design (SBCCI) and Congress of the Brazilian Microelectronics Society (SBMIcro). Past President of the Brazilian Computer Society and Past Vice-President of the Brazilian Microelectronics Society. IEEE CASS Chapter Rio Grande do Sul Chair (since 2007). Vice-president of IEEE Circuits and Systems representing R9, for two terms, from 2008 to 2011. Chair of IFIP TC10. Member of the Editorial Board of IEEE Design&Test and IEEE JETCAS. Member of the Steering Committee of the following conferences: IFIP/IEEE VLSI-SoC, ICECS, LASCAS, NEWCAS, IEEE CASS Summer School, IEEE ISVLSI, SBCCI, PATMOS, IBERCHIP. Ricardo Reis is a senior member of IEEE.

  • Ministrante: Sarma Vrudhula

  • Instituição do Ministrante: Arizona State University

  • Biography: Sarma Vrudhula is a Professor of Computer Science and Engineeringat Arizona State University, Tempe AZ, and the director for the NSFI/UCRC Center for Embedded Systems. Prior to joining ASU, he has held faculty positions in ECE at the University of Arizona, and at the University of Southern California. He was the founding Director of the NSF Center for Low Power Electronics as the University of Arizona.
    He is a IEEE Fellow for “contributions to low power and energy-efficient design of digital circuits and systems''. Active research areas include: threshold logic based digital design, new circuit architectures with emerging technologies for non-volatile computation; energy management of mobile systems; statistical methods for the analysis and optimization with of process variations. He holds a Bachelor of Mathematics degree from the University of Waterloo, Ontario, Canada, and an MSEE and Ph.D. degrees in Electrical and Computer Engineering from the University of Southern California.

    Lecture: This talk will present new approaches to reduce the dynamic power, leakage, and area of application-specified integrated circuits (ASICs), without sacrificing performance. Two different but additive methods that are based on the use of sense-amp (SA) based flipflops are described. The first approach employs a set of enhanced SA based flipflops referred to as threshold logic flipflops (TLFF), which that can be configured to realize subset of multi-input Boolean functions known as threshold functions. The design of TLFFs and an algorithm to seamlessly integrate them into existing ASIC design flow is described. Post P&R experimental results and measurements from manufactured prototypes demonstrate significant reductions in power, leakage, and area using the proposed methodology. The second approach uses SA-based flipflops to deliberately skew the clock some certain flipflops without the use of additional clock buffers. This is done by having some flipflops, called “sources”, generate clock signals for other flipflops, called “targets”. An algorithm is described that identifies the sources and targets involved in the new clocking scheme, with the objective of reducing area and power. Deliberate clock skewing without the use of additional buffers also results in significant improvements in power and area. The combination of both approaches results in substantial improvements in power, leakage, area and wire-length without sacrificing performance.

  • Ministrante: Carlos Galup

  • Instituição do Ministrante: UFSC

  • Biography: Carlos Galup-Montoro studied engineering sciences at the University of the Republic, Montevideo, Uruguay, and electronic engineering at the National Polytechnic School of Grenoble (INPG), France. He received an engineering degree in electronics in 1979 and a doctorate degree in 1982, both from INPG. From 1982 to 1989 he was with the University of São Paulo, Brazil, where he was engaged in junction field effect transistor (JFET) fabrication and analog circuit design. Since 1990, he has been with the Electrical Engineering Department, Federal University of Santa Catarina, Florianópolis, Brazil where he is now a professor. In the second semester of the academic year 1997/98 he was a research associate with the Analog Mixed Signal Group, Texas A&M University. In the academic year 2008 /09 2009 he was a visiting scholar at UC Berkeley. He is coauthor of the textbooks: “MOSFET Modeling for Circuit Analysis and Design”, World Scientific, 2007 and “CMOS Analog Design Using All-Region MOSFET Modeling”, Cambridge University Press, 2010.

    Lecture: Since the MOS transistor is the basic component of modern electronics, a careful presentation of its basic theory will be given. Instead of the usual approach of furnishing separate analytical formulas for the strong and weak inversion regions of the MOS transistor, we provide simple formulas which are valid in all operating regions, including moderate inversion. We will review ultra-low-power circuits that allow the automatic extraction of the specific current IS and the threshold voltage VT of MOS transistors, which are fundamental parameters for circuit design and testing, as well as for technology characterization. The design of this class of circuits must be based on all-region MOSFET models since both the drift and the diffusion components of the drain current are important for transistors operating near the threshold condition.

4 DE MAIO, SEXTA-FEIRA

  • Ministrante: Cláudio Diniz

  • Instituição do Ministrante: UCPel
  • Ministrante: Alyssa Apsel

  • Instituição do Ministrante: Cornell University

  • Biography: Alyssa Apsel is currently a Professor of Electrical and Computer Engineering and a Visiting Professor at Imperial College in London working on RF interfaces for implantable electronics. She received the B.S. from Swarthmore College in 1995 and the Ph.D. from Johns Hopkins University, Baltimore, MD, in 2002. She joined Cornell University in 2002, where the focus of her research is on power-aware mixed signal circuits and design for highly scaled CMOS and modern electronic systems. Her current focus is on low power radio for IoT and reconfigurable multi-standard radio to extend the reach of wireless communications. She has authored or coauthored over 100 refereed publications in related fields of RF mixed signal circuit design, ultra-low power radio, interconnect design and planning, photonic integration, and process invariant circuit design techniques resulting in eight patents and several pending patent applications. She received best paper awards at ASYNC 2006 and IEEE SiRF 2012, had a MICRO “Top Picks” paper in 2006, received a college teaching award in 2007, received the National Science Foundation CAREER Award in 2004, and was selected by Technology Review Magazine as one of the Top Young Innovators in 2004. She has also served as an Associate Editor of various journals including IEEE Transactions on Circuits and Systems I and II, as the chair of the Analog and Signal Processing Technical committee of ISCAS 2011, as Deputy Editor in Chief of Circuits and Systems Magazine, and on the Board of Governors of IEEE CAS.

    Lecture: Over the past decades the world has become increasingly connected, with communications driving both markets and social movements. Low power electronics, efficient communications, and better battery technology have all contributed to this revolution, but the cost and power required for these systems must be pushed further to make cheap, ubiquitous, seamless communication accessible to a wider community. In this talk I will discuss two engineering approaches to this problem. I will look at various approaches to drive the power down in radio networks that span across circuits and systems. I will also look at creative biologically inspired approaches to enabling very low power networks and IoT. Finally, I will discuss how by adding flexibility and building reconfigurable hardware, we can likewise build lower power and less costly consumer systems that can adapt across protocols and networks and work under changing device technologies.

  • SIM 1 - Communications Circuits & Systems I
  • 14:00 – 14:15: Inverse Problem Applied to the Validation of Digital Pre-distorters for Power Amplifiers. Caio Phillipe Mizerkowski, Eduardo Gonçalves de Lima.
  • 14:15 – 14:30: Reconfigurable CMOS Power Amplifier for Efficiency Improvement. Favero Santos, Jonathas Pereira, Bernardo Leite, Andre Mariano.
  • 14:30 – 14:45: A Three-layer Perceptron Tailored for the Joint Modeling of I/Q Modulator Impairments and Power Amplifier Distortions. Luiza Freire, Bruna Marcondes, Eduardo Lima.
  • 14:45 – 15:00: Effect of Nakagami-m Fading on the Scalability of LoRa/LoRaWAN Networks. Felipe Honório, Glauber Brante, Guilherme Moritz, Mario de Noronha Neto, Arliones Hoeller, Richard Demo Souza.
  • 15:00 – 15:15: Layout-oriented Design of a 60 GHz Power Amplifier in SiGe. Elmo Sette, Antonio Souza, Emmanuel Dupouy.
  • 15:15 – 15:30: Reliability of Components in Power Amplifiers Based in MIL-HDBK-217F Standard. Carlos Silva, Edson Santos.


  • SIM 2 - Circuits & Systems for Signal and Image Processing
  • 14:00 – 14:15: Using Efficient Adder Compressors with a Split-Radix Butterfly Hardware Architecture for Low-Power IoT Smart Sensors. Gustavo Santana, Guilherme Paim, Leandro Rocha, Renato Neuenfeld, Mateus Fonseca, Eduardo Costa, Sergio Bampi.
  • 14:15 – 14:30: A Neural Network to Brazilian License Plate Detection. Arthur Sofiatti, Fabio Pereira, Altamiro Susin.
  • 14:30 – 14:45: Exploiting Absolute Arithmetic for Power-Efficient Sum of Absolute Differences. Brunno Abreu, Guilherme Paim, Mateus Grellert, Bianca Silveira, Cláudio Diniz, Eduardo Costa and Sergio Bampi.
  • 14:45 – 15:00: Using Adder and Subtractor Compressors to Sum of Absolute Transformed Differences Architecture for Low-Power Video Encoding. Guilherme Paim, Bianca Silveira, Brunno Abreu, Mateus Grellert, Rafael Ferreira, Cláudio Diniz, Eduardo Costa and Sergio Bampi.
  • 15:00 – 15:15: Quantitative Analysis of Image Acquisition Using Mammographic Phantom with Silicone Prosthesis. Rafaela Monteiro Soares, Kaiser Kruger, Michel Pinheiro Madruga, Lenita Franz Bezerra, Luana Schulz, Matheus Stigger, Everton Granemann Souza, Ana Cláudia Patrocinio, Chiara Das Dores Nascimento.
  • 15:15 – 15:30: Voice Activity Detection Algorithm based on Kernels using Unsupervised Segmentation. Aminadabe Dos Santos Pires Soares, Wemerson Delcio Parreira, Chiara Das Dores Nascimento, Everton Granemann Souza.


  • SIM 3 - Embedded Systems and System-on-Chip Design
  • 14:00 – 14:15: Analysis of Classification Algorithms for Hand Gesture Recognition. Felipe Quirino, Marcelo Romanssini, Alessandro Girardi.
  • 14:15 – 14:30: System Implementation of a Glove for Hand Gesture Detection. Marcelo Romanssini, Felipe Quirino, Alessandro Girardi
  • 14:30 – 14:45: Exploring Fog-Computing for Context Awareness in EXEHDA Middleware. Verônica Maurer Tabim, Leonardo Rosa S. João, Cláudio Machado Diniz, João Ladislau B. Lopes, Rodrigo Santos de Souza, Adenauer Corrêa Yamin.
  • 14:45 – 15:00: Using Interlocked Hardware Microkernel to Boost the Processing Performance of Task-Based Systems. Leandro Dantas, Salvador Gimenez.
  • 15:00 – 15:15: Implementation of SIMON Block Cipher to Provide Confidentiality to a Network-on-Chip. Antonio Frederico Mellies Neto, Eduardo Alves Da Silva, Fabricio Bortoluzzi, Cesar Albenes Zeferino.
  • 15:15 – 15:30: A Low-Cost Embedded System for Traffic Monitoring in Urban Roads. Lucas Rebello, Filipe Capella, Cesar Zeferino.
  • Ministrante: Ronald Valenzuela, Synopsys Chile R&D Center

  • Biography: Ronald is an Electronics Engineer from Universidad de Concepción (Concepción, Chile), he also holds a Graduate Certificate on Electronic Circuits from Stanford University (Stanford, CA). He currently manages a team of Application Engineers (A.E.) specialized in Multi Voltage Implementation Tools, covering optimization during Logic Synthesis and Place & Route. As A.E. he provides technical support to field engineers regarding tool and low power methodologies using Synopsys products, they also ensure product quality by performing functional tests using industrial design flows and they collaborate with developers to define requirements for product enhancements.

    Lecture: Predicted by Moore on 1965, circuit integration capacity has reached the scale of billion synchronized transistors. At this scale, we can only manage system complexity thanks to software automation, which through synthesis, allows us to behaviorally describe a circuit and convert it into a network of logic gates that we can fit into silicon. This talk will discuss modern techniques applied during logic and physical synthesis of circuits, from a designer’s perspective. Talk will cover basics, circuit optimizations, handling of interconnections and physical synthesis.

  • Ministrante: Ricardo Jasinski, Solvis

5 DE MAIO, SÁBADO

  • SIM 4 - Communications Circuits & Systems II
  • 08:30 – 08:45: Incremental and Decremental Approaches to Reduce the Number of Parameters in Polynomial Models. Luis Schuartz, Edson Santos, Bernardo Leite, André Mariano, Eduardo Lima.
  • 08:45 – 09:00: Traditional and Saturated Digital Baseband Predistorters for Wireless Transmitters. Luis Schuartz, Edson Santos, Bernardo Leite, André Mariano, Eduardo Lima.
  • 09:00 – 09:15: Energy Efficiency Optimization in Wireless Sensor Networks with Latency and QoS Constraints. Erich Heilmann, Guilherme Moritz, Glauber Brante, Richard Souza.
  • 09:15 – 09:30: A Single Measurement Based Iterative Process for Identification of IQ Compensator and PA Predistorter. Bruna Marcondes, Eduardo Lima.
  • 09:30 – 09:45: A Modified Polar Volterra Series for the Behavioral Modeling of Radio Frequency Power Amplifiers for Wireless Communication Systems. Ricardo Cavalheiro, Eduardo Lima.
  • 09:45 – 10:00: Linearity characterization of a multimode CMOS Power Amplifier for IEEE 802.11n, IEEE 802.11ax and LTE signals. Arthur Amorim Modesto, Fávero Guilherme Santos, Bernardo Rego Barros de Almeida Leite, André Augusto Mariano.


  • SIM 5 - Digital Circuits
  • 08:30 – 08:45: Petri Nets in Reconfigurable Logic Hardware - Implementing Petri Nets using FPGAs. Perci Ayres Antiqueira, Carlos Raimundo Erig Lima, Jean Marcelo Simão.
  • 08:45 – 09:00: Exploring Carry Acceleration Structures in Multi-bit Adders. Thomas Fontanari, Gustavo Santana, Guilherme Paim, Leandro Rocha, Eduardo Da Costa, Sergio Bampi
  • 09:00 – 09:15: Study and Characterization of Multilayered Organic Devices for Field-Effect Transistors. Natalia Pereira Menezes, Fabiano Thomazi, César Augusto Dartora.
  • 09:15 – 09:30: Area and Power Optimization of Single-Stage Architectures of the Fast Fourier Transform using Multiple Constant Multiplication. João G. Nizer Rahmeier, Eduardo A. C. Costa, Alessandro Girardi, Sidinei Ghissoni.
  • 09:30 – 09:45: Exploring the Use of Parallel Prefix Adder Topologies into Approximate Adder Circuits. Morgana Macedo Azevedo Da Rosa, Leonardo Bandeira Soares, Bianca Silveira, Cláudio Diniz, Eduardo Da Costa.
  • 09:45 – 10:00: Comparing 4-bits Adders Topologies on 32nm. Albano Borba, Vagner Rosa, Cristina Meinhardt


  • SIM 6 - Analog, Mixed-Signal and Communications Circuits
  • 08:30 – 08:45: Transformers Layout Configurations Analysis Through Electromagnetic Simulations. Rodrigo Godinho Silva, Bernardo Rego Barros de Almeida Leite, Andre Augusto Mariano.
  • 08:45 – 09:00: A Systematic Methodology for Operational Amplifiers Experimental Measurements. Luiz Antônio Da Silva Jr., Anderson Fortes, Robson Domanski, Paulo Comassetto, Alessandro Girardi.
  • 09:00 – 09:15: Switched capacitors filters using CMOS technology. Thiago Freitas, Luis Lolis.
  • 09:15 – 09:30: Envelope Methods Applied to Simulation of Power Amplifiers with Efficiency Enhancement Techniques. Luis Schuartz, Edson Santos, Bernardo Leite, André Mariano, Eduardo Lima
  • 09:30 – 09:45: Mixed Learning Architecture for Identification with Reduced Sampling Frequency of Digital Baseband Predistorters based on Three-layer Perceptrons. Joel Chavez, Caio Mizerkowski, Eduardo Lima
  • 09:45 – 10:00: Optimization of a CMOS Operational Amplifier Using an Interactive Evolutionary Algorithm. Rodrigo Moreto, Carlos Thomaz, Salvador Gimenez.
  • SIM 7 - Electronic Design Automation
  • 10:30 – 10:45: Temperature Variability and Transistor Sizing Impact in MOSFET Characteristics. Lucas Custodio, Paulo F. Butzen.
  • 10:45 – 11:00: Evaluation of Variability Through Schmitt Trigger Technique on CMOS Full Adder Layout. Leonardo Moraes, Alexandra Zimpeck, Cristina Meinhardt, Ricardo Reis.
  • 11:00 – 11:15: Two-stage OTA Sizing Optimization Using Bio-Inspired Algorithms. Anderson Fortes, Luiz Antônio Da Silva Jr., Robson Domanski, Alessandro Girardi
  • 11:15 – 11:30: Framework-based Arithmetic Core Generation to Explore ASIC-based Parallel Binary Multipliers. Leandro Mateus Giacomini Rocha, Guilherme Paim, Gustavo Santana, Eduardo Costa, Sergio Bampi.
  • 11:30 – 11:45: Evaluation of Trunk Routing Heuristics Applied to Detailed Routing. Eder Monteiro, Mateus Fogaça, Henrique Placido, Jucemar Monteiro, Isadora Oliveira, André Oliveira, Guilherme Flach, Marcelo Johann, Ricardo Reis.
  • 11:45 – 12:00: A Named-Pipe Library for Hardware Simulation. Bruno Bonotto, Ismael Seidel, Luiz Henrique Cancellier, Marcio Monteiro, José Luís Güntzel


  • SIM 8 - Circuit Analysis, Variability and Fault Tolerance
  • 10:30 – 10:45: The Effects of Resistive Defects in FinFET SRAMs. Thiago Copetti, Guilherme C. Medeiros, Leticia Bolzani Poehls, Tiago Balen.
  • 10:45 – 11:00: Implementation of Fault Tolerance Techniques in an Integrated Network Interface. Thalyson Silva, Lucas Pereira, Douglas Melo, Cesar Zeferino, Eduardo Bezerra.
  • 11:00 – 11:15: Analyze of Permanent and Transient Faults in 6T SRAM cell. Cleiton Magano Marques, Roberto Almeida, Cristina Meinhardt, Paulo Butzen.
  • 11:15 – 11:30: PVT variation impact on 16nm SRAM cells. Roberto Almeida, Paulo F. Butzen, Cristina Meinhardt
  • 11:30 – 11:45: Investigating Schmitt Trigger Inverters behavior at 16nm technologies. Clayton Farias, Samuel Toledo, Cristina Meinhardt, Paulo F. Butzen.
  • 11:45 – 12:00: 16nm XOR behavior under PVT variability: Tri-Gate versus bulk CMOS. Fábio Gustavo Rossato Gomes Da Silva, Cristina Meinhardt, Ricardo Augusto Da Luz Reis


  • SIM 9 - Communications Circuits & Systems III
  • 10:30 – 10:45: Reconfigurable 2.4 GHz CMOS power amplifier with integrated transformer-based power combiner. Joao Paulo Perbiche, Leila Deng, Favero Santos, Bernardo Leite, Andre Mariano.
  • 10:45 – 11:00: Evaluation of a discrete-time filterbank performance with fixed point arithmetic for clock skew compensation in time-interleaved-analog-to-digital-converters. Anderson Luiz, Luis Lolis.
  • 11:00 – 11:15: Fixed-point VHDL Description of a Look-up Table Based Combined Memory and Envelope Memory Polynomial Model. Isabella Wosniack, Émeli Silveira, Felipe Schoulten, Sibilla França, Eduardo Lima.
  • 11:15 – 11:30: Fixed-point Arithmetic Description of Limiting and Filtering for Peak-to-average Power Ratio Reduction. Felipe Schoulten, Isabella Wosniack, Felipe Yasuda, Sibilla França, Eduardo Lima.
  • 11:30 – 11:45: Multimode 2.4 GHz CMOS Power Amplifier with Gain and Power Control. Bruno Tarui, Fávero Santos, Edson Santos, Bernardo Leite, André Mariano.

ORGANIZAÇÃO


Coordenação Geral
André Augusto Mariano (UFPR)
Eduardo Gonçalves de Lima (UFPR)
Coordenação do programa SIM
Cláudio Machado Diniz (UCPel)
Bernardo Leite (UFPR)
Coordenação do programa EMICRO
Oscar da Costa Gouveia Filho (UFPR)
Raphael Martins Brum (UFRGS)
Coordenação Local
Sibilla Batista da Luz França (UFPR)
Waldomiro Soares Yuan (UFPR)
Coordenação Financeiro
José Rodrigo F.Azambuja (UFRGS)
Luis Henrique Assumpção Lolis (UFPR)
Coordenação IEEE CASS
Ricardo Reis (UFRGS)

LOCAL

CENTRO POLITÉCNICO - UNIVERSIDADE FEDERAL DO PARANÁ





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